Search - FPGA DDS

[VHDL-FPGA-Verilog] dds

Description: 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Platform: | Size: 468992 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] vhdl-dds

Description: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Platform: | Size: 88064 | Author: martin | Hits:

Description: DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental increase, so it can be said of the frequency switching time is the frequency control word transmission time,
Platform: | Size: 2096128 | Author: lqb | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Platform: | Size: 560128 | Author: 陈阳 | Hits:

[SCM] DDS

Description: 利用FPGA的资源实现任意波形的产生，再若和单片机配合就能做成任意的波形发生器。-Use of FPGA resources for the realization of arbitrary waveform generation, again if and SCM can be made with the arbitrary waveform generator.
Platform: | Size: 520192 | Author: 张军 | Hits:

[Software Engineering] dds

Description: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Platform: | Size: 1695744 | Author: 姜兆刚 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS原理介绍，里面是有时序图和系统设计！-DDS principle that there is a timing diagram and system design!
Platform: | Size: 454656 | Author: dragon | Hits:

[Software Engineering] dds

Description: dds移相信号发生器 VHDL语言代码-dds
Platform: | Size: 384000 | Author: hanoi | Hits:

[VHDL-FPGA-Verilog] sum_ten

Description: 十位累加器,EDA,FPGA,DDS信号发生器的相位累加器,可用.-Accumulator 10, EDA, FPGA, DDS signal generator of the phase accumulator can be used.
Platform: | Size: 3072 | Author: seasonroad | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计-FPGA, vhdl language learning materials FPGA design of a simple design dds
Platform: | Size: 2098176 | Author: wade | Hits:

[VHDL-FPGA-Verilog] 32_hottest_forum_CPLD-FPGA

Description: 收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.
Platform: | Size: 13312 | Author: 张芸 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
Platform: | Size: 1086464 | Author: liulei | Hits:

[VHDL-FPGA-Verilog] FPGA-basedhigh-performance32-bitfloating-pointnucl

Description: 基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga
Platform: | Size: 7507968 | Author: bonjour | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[Books] dds

Description: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Platform: | Size: 1442816 | Author: 王勤 | Hits:

[Special Effects] VIDEO-FPGA

Description: 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
Platform: | Size: 6034432 | Author: 王刚 | Hits:

[Software Engineering] FPGA

Description: 为了满足科研与实验需要,提出并实现了一种以FPGA和高速D/A为核心,其结构简单,控制灵活,信号质量高的多功能信号源生成系统。该信号源生成系统能够实时产生中心频率在30~130 MHz的各种雷达、通信、导航和白噪声等信号,且产生的各种信号频率、幅度、相位和其他参数均可控。信号源作为基带信号单元配以混频模块,可实现在任意频段的信号。另外,该信号源还可以作为一个通用平台,通过FPGA内部程序的更新来实现其他复杂信号。-This paper presents and makes a multi-functional signal source based on FPGA and high speed D/A which has simple configuration,flexible controlling,and top-quality signals to satisfy needs of the scientific research and experiment.This signal source can generate several signals as radar signals,communication signals,navigation signals,noise signals and so on.These signals have center frequency between 30~130 MHz,its frequency,power,phase and other parameters are adjustable.This signal source can also ...
Platform: | Size: 330752 | Author: 将建 | Hits:

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[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] vhdl-dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[SCM] DDS

[Software Engineering] dds

[VHDL-FPGA-Verilog] DDS

[Software Engineering] dds

[VHDL-FPGA-Verilog] sum_ten

[VHDL-FPGA-Verilog] FPGA

[VHDL-FPGA-Verilog] 32_hottest_forum_CPLD-FPGA

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGA-basedhigh-performance32-bitfloating-pointnucl

[VHDL-FPGA-Verilog] DDS

[Books] dds

[Special Effects] VIDEO-FPGA

[Software Engineering] FPGA

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

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